Metal-oxide semiconductor field effect transistor (MOSFET) and the various methods of manufacturing are well known in the art. For economic reasons, the dimensions of the individual device, or circuit, are to be made as small as possible, so that more circuits can be squeezed in one chip, and that more dies can be formed in a single wafer. Therefore, the trend in the semiconductor industry is to increase the dimension of the wafer while, at the same time, reduce the dimension of individual semiconductor devices.
During such a drive to miniaturization, the gate lengths of MOSFETs are increasingly made to be narrower. However, if we merely decrease the gate length but keeping all other design conditions the same, some problems will be experienced. As shown in FIG. 1A, the channel (i.e., the distance between the source and drain) will overlap with the depletion regions of source and drain; this will lead the so-called short channel effect and increase the sub-threshold current I.sub.d. Both conditions can cause adverse effects are highly undesirable.
The sub-threshold current I.sub.d is defined as the current passing through the channel from drain to source when the gate voltage is smaller than the threshold voltage specific to a device. In other words, the sub-threshold current is the current which exists when the MOSFET is "Off".
The movements of carriers in a semiconductor circuit can be categorized into two modes: the drifting mode and the diffusion mode. The first mode is caused by an electrical field; whereas, the second mode is related to the temperature of the carriers. Using an N-type MOSFET as an example, the movement of the carriers is under the drifting mode when the gate voltage is greater than the threshold voltage. On the other hand, when the applied gate voltage is lower than the threshold voltage, the movement of carriers will be switched to the diffusion mode. By the nature of carrier movement, the NMOS can be considered as an equivalent of an npn Bipolar Junction Transistor (BJT) constructed having the structure of "source-channel-drain", whose PN junction between source and channel is under a forward bias and whose junction between channel and drain is under a reverse bias so that the NMOS under the condition of diffusion mode is operated as an acting mode npn BJT. And electrons will flow from source to drain. The sub-threshold current I.sub.d is the sum of all these moving electrons.
FIG. 1B shows sub-threshold current I.sub.d as a function of gate voltage under various gap width (i.e., channel length) conditions. FIG. 1B clearly shows that, as channel length decreases, the sub-threshold current I.sub.d increases. Under the operating conditions underlying the FIG. 1B test results, it can be seen that, when the channel length is less than 1 .mu.m, the sub-threshold current will experience a rapid increase and large amounts of electrons will be drifting from the source into the channel. This situation causes the operation mode of the NMOS to approach or even become an active mode, even though the gate voltage is still substantially smaller than the threshold voltage. This means that the gate electrode has lost its ability of serving as a control switch.
The technique of high-concentration doped region substrate has been applied in an attempt to solve the above-mentioned problem by limiting the extent of the depletion region from which electrons can be diffusing into the channel. Another research direction for reducing the sub-threshold current is to minimize the cross-sectional area of the channel, based on the direct proportional relationship between the sub-threshold current I.sub.d and the cross-sectional area of the channel. This had led to a new class of diffusion techniques for manufacturing semiconductor devices called "Shallow Junction MOSFET Manufacturing" technique.
Although the application of shallow junction techniques can solve the problem of high sub-threshold current I.sub.d under the conditions of reduced channel length, some other drawbacks have, however, surfaced which mainly involve the problems associated with the contact hole forming and the salicide (self-aligned silicide) process. With the shallow junction technique, the source/drain regions are vulnerable to chemical attacks during the contact hole etching and salicide formation. For the ultra shallow junctions, the over-etching will cause a concaved bowl in the junction and allow the contact plug to be too close to the junction edge. This causes the leakage current to increase. Moreover, the shallow junction technique also always poses the risks that it may etch through the junction and thus destroy the transistor.
The most directive approach at the present time is to deposit a buffer conductive layer on the source/drain regions to increase the thickness thereof. In an article entitled "A High-Performance 0.1 .mu.m CMOS with Elevated Salicide using Novel Si-SEG Process," by Hitoshi Wakabayashi, Toyoji Yamamoto, Toru Tatsumi, Ken'ichi Tokunaga, Kakao Tamura, Tohru Mogami, and Takemitsu Kunio, IEDM (1997), it was demonstrated that a selective epitaxial growth (SEG) process can be used to form a raised source/drain device. The SEG process employed by these authors was carried out under reaction conditions of 600.about.650.degree. C., with 1.about.2 SCCM Si.sub.2 H.sub.6 gas.
While the SEG process may offer an alternative approach to fabricate raised source/drain regions, the equipment of SEG is not a mass production equipment and that most IC fabs do not have the SEG equipment. Thus, from the above discussions, it is apparent that a raised source/drain regions MOSFET manufacturing process with a mass product capability is desired as an ultra-sub-micron semiconductor technique. Further, as the shallow junction technique is applied on the type of semiconductor devices such as CMOS, flash memory, and EEPROM, the process for raising doped regions will become in greater demand.